The present invention relates generally to memory cells and more specifically to the use of amorphous devices as non-volatile fast read and write random access memories. The use of amorphous semiconductor devices as memory cells is well known. The time generally required to establish the low resistance state of an amorphous memory is in the order of a few milliseconds. Thus, amorphous memory cells have generally been slow write and are considered to be electrically alterable read only memories (EAROM).
The mechanism of writing in an amorphous layer is the growth of crystal around the hot conducting constant voltage filament that conducts the write current. The hot channel is eventually suppressed by current stealing of the growing crystallites. The appearance of the low resistance state is discontinuous in time and this can be accounted for by a combination of the unique discontinuous electrical conductivity characteristics of conductor-dielectric mixtures and the fact that the micro crystallites are growing in glass at elevated temperatures.
The continuous switching of amorphous devices between the high and low resistance states produces an amorphous structure of varying "offness" and "onness". These degrees of "onness" and "offness" have been recognized by U.S. Pat. No. 3,418,619 to P. E. Lighty and U.S. Pat. No. 3,448,302 to D. J. Shanefield. The operation of the device, depending on the degree of "onness" or "offness," are discussed in these patents and are considered an undesirable effect. The Lighty patent suggests using a small diameter elongated filament structure as a solution of the problem. Shanefield's approach to the problem is to use an adaptive system which monitors the degree of "offness" or "onness" and modifies the current or voltage to achieve the desired results. Shanefield measures the degree of "offness" by measuring the threshold level breakdown voltage of the device. Once a critical threshold value has been passed, corrective measures are taken to increase the "onness" of the device. Thus, Lighty and Shanefield, realizing the variance of threshold value with the degree of "onness", operate to correct this state such that the amorphous memory may be operated between the two desired states, namely a high resistance state and a low resistance state. The operation of these two devices are considered to be slow as functioning in the millisecond range for writing.
The relationship of the threshold voltage levels and the resistance is illustrated in FIG. 1. As can be seen, the appearance and growth of crystallites during the early stage of the write are not easily detectable by changes in the device conductance or resistance, but they do shorten the dielectric path between the electrodes and reduce the switching or threshold voltage. Therefore, from the moment that the crystal growth starts, the threshold voltage is decreasing. This phenomenon is described in "The Switching Mechanisms in Amorphous Chalcogenide Memory Devices," A. G. Steventon, Journal of Non-Crystalline Solids, 21 (1976) 312-329, (North Holland Publishing Co.).